1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for processing interrupts. Still more particularly, the present invention relates to a method, apparatus, and computer instructions for managing interrupts using multiple processors.
2. Description of Related Art
Interrupt handling mechanisms have been developed for more effectively dealing with input/output transactions between a processor and a peripheral device connected to the processor. Whenever a peripheral device requires processor support as part of an input/output (I/O) operation, the device sends an interrupt signal to the processor to notify that an interrupt condition exists in the peripheral device. Depending on the type of interrupt signal received, the processor may elect to ignore the interrupt and finish the current process or handle the interrupt when the signal is received. Once the interrupt signal is handled by the interrupt handling mechanism, the processor returns to the previous state that was present before the interrupt occurred. An interrupt source may be, for example, a keyboard, an adapter, or any other device connected to the processor.
The processing of an interrupt request typically involves the processor interrogating the source of the interrupt, performing specific functions based on the type of interrupt, and finally, resetting or turning off the interrupt request. Several different types of interrupt requests exist. For example, when an interrupt request is deferred by the processor, the interrupt request is referred to as a masked request. Another type of interrupt request may also be prioritized by a particular system, if the request from one device is more urgent than a request from another device. Thus, the request from one device is considered to have priority over the request from the other device. The priority of an interrupt request is predefined in the data processing system. When an interrupt request has been accepted by a processor, a subsequent interrupt request cannot interrupt the current interrupt request unless the subsequent interrupt request has priority over the current interrupt request. If the subsequent interrupt request does not have priority, then the subsequent interrupt request waits until the current request is handled.
As data processing systems become more complex, containing more peripheral devices, the increasing number of interrupt requests generated by these devices slow down the processor. As a result, interrupt controllers have been developed to delegate certain interrupt functions from the processor to the interrupt controller. These interrupt controllers allow the processor to continue working without having to service an interrupt request at the time the request is first made. The interrupt controller is used to monitor interrupt sources, while only interrupting the processor using a single interrupt line.
These types of interrupt controllers were initially developed for use within a single processor data processing system. This type of interrupt subsystem typically had few interrupt sources or priority levels. With the introduction of multi-processor data processing systems, more than one processor within this type of system is capable of handling an interrupt request. However, an interrupt signal for each interrupt source has to be wired to each processor or interrupt controller capable of servicing an interrupt to allow those processors to handle these interrupt requests. Such an architecture leads to increases in bus complexity, because of the number of interrupt signals that have to be hardwired to each processor in the system.
In response, dedicated interrupt controllers have been provided for each processor in a data processing system. This kind of approach, however, is costly and does not allow for effective management of interrupts as the number of interrupt sources and priority levels increase.
Another type of interrupt subsystem provides for queuing of interrupts from many sources and presenting interrupts to the processor bus in the multiprocessor system. The selection of the processor to interrupt is accomplished by separating the internal interrupt mechanism into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service or process the interrupt. By providing two layers within the interrupt subsystem, application or system software may be written, which is independent from the specifics of the processor selection mechanism used by the interrupt routing layer. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software and provides hardware independent functionality. Interrupt lines from the various interrupt sources are input into an interrupt source controller. This interrupt source controller is connected using a fabric, such as a bus, which also is connected to the interrupt presentation controllers.
Interrupt presentation controllers are used to present interrupts to the processors in the data processing system. Each processor in the data processing system is associated with a memory mapped interrupt management area. Some implementations distribute the interrupt presentation layer by placing the interrupt management areas for some of the platform processors in one chip and the interrupt management areas of the rest of the processors in other chips.
Placement of the interrupt management area on different chips occurs because of the impracticality of integrating the interrupt presentation controller for all system processors within a single chip. However, when the interrupt management areas are implemented on different chips, interrupt messages may have to be forwarded between implementing chips if no accepting processor can be found in the original presentation layer chip.
Furthermore, if a priority-based assignment is implemented in an interrupt subsystem, then the priority of the least favorite processor may be broadcast to the other presentation layer chips. These methods for allowing the proper assignment of interrupt requests to multiple interrupt presentation controllers are currently complex and/or require significant amounts of specialized signal wires between the multiple controllers.
The interrupt subsystem is often required to aggregate the sub-set of processors from the total number of processors in a data processing system into a group server pool. Within this group server pool is a group of processors in which any available processor is able to handle a given interrupt request. The interrupt subsystem is required to deliver interrupts to one of the available processors within the group.
Shortcomings in these types of interrupt subsystems involve the use of a central collection of logic that stores the identification of processors selected for handling interrupts. The problem with this type of interrupt subsystem is that the central collection of logic has to increase in size and complexity as the total number of processors that are supported grows. As a result, the central collection of logic becomes large and expensive having to be sized for the maximum number of processors that the system can support, even though most systems are not that large. Further, this central collection of logic also becomes a single point of failure for the entire interrupt subsystem. As a result, duplication or redundancy is required to guard against such failures.
In another type of interrupt subsystem architecture, interrupts are directed to all processors in the system until a processor is selected. Such a system encounters a problem because interrupt messages must be directed to interrupt controllers that have no potential for being candidates for taking interrupt requests. As a result, an excess load is generated on those interrupt controllers. Further, for each interrupt condition, interrupt messages on average circulate about 1.5 times around all the interrupt controllers and in many cases, more often. As a result, excess message traffic is placed on the busses within the data processing system. Additionally, certain processors may tend to receive more interrupt requests than other processors. These processors are typically ones handling background work. As a result, the background work is penalized by sending interrupts to those processors.
Therefore, it would be advantageous to have an improved method, apparatus, and computer instructions for handling interrupts in the data processing system.